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High Performance CMOS Phase Locked Loop For Ubiquitous Network 800MHz ISM Band

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3 Author(s)
In Ho Hwang ; Univ. of Ulsan, Ulsan ; Byung Min Lee ; Jong Hwa Lee

In this paper proposed the high performance PLL for ubiquitous network 800 MHz ISM band. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. CP (Charge Pump) and LP (Loop filter) is consisted of Negative feedback and current reuse circuit in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with S-stage differential ring oscillator is used to obtain exact output frequency. The divider is consisted of D-type flip flops asynchronous divider. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 500 MHz to 1.1 GHz and has 1.8 GHz/v of voltage gain. The proposed PLL is based on 0.18 mum CMOS technology with 1.8 V supply voltage. PLL input frequency is 25 MHz and VCO output frequency is 800 MHz. The proposed PLL lock time is 6.5 us. It is evaluated by using cadence spectra RF tools.

Published in:

Electron Devices and Materials, 2007. EDM '07. 8th Siberian Russian Workshop and Tutorial on

Date of Conference:

June 1 2007-July 5 2007