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Pipelined Architecture for High-Speed Implementation of Multilevel Lifting 2-D DWT using 9/7 Filters

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2 Author(s)
Mohanty, B.K. ; Jaypee Inst. of Eng. & Technol., Guna ; Meher, P.K.

In this paper, we present a pipeline architecture for high-throughput VLSI implementation of multilevel two-dimensional (2-D) discrete wavelet transform (DWT). The computation of each decomposition level is decomposed into two distinct stages, and implemented concurrently in a linear array of fully-pipelined processing elements (PE). The main advantage of the proposed design is that it does not involve any off-chip storage, and involves less than (N/4) times normalized on-chip storage compared with the best of the existing structures. Moreover, it offers nearly (N/3) times higher throughput rate at the cost of marginally higher normalized number of multipliers and adders per throughput compared to those of the existing folded structures for lifting-based 2-D DWT. In comparison with the existing designs based on the recursive pyramid algorithm (RPA), the proposed one offers (N/4) times higher computation rate. Moreover, the normalized number of multipliers and adders of the proposed structure is less than those of corresponding existing structures.

Published in:

Signals, Circuits and Systems, 2007. ISSCS 2007. International Symposium on  (Volume:1 )

Date of Conference:

13-14 July 2007