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Transactional Memory: An Overview

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7 Author(s)

Writing applications that benefit from the massive computational power of future multicore chip multiprocessors will not be an easy task for mainstream programmers accustomed to sequential algorithms rather than parallel ones. This article presents a survey of transactional memory, a mechanism that promises to enable scalable performance while freeing programmers from some of the burden of modifying their parallel code.

Published in:

Micro, IEEE  (Volume:27 ,  Issue: 3 )

Date of Publication:

May-June 2007

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