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This paper describes the implementation of a number of HPC accelerators on FPGAs. The methodology and tools used for their implementation is the same as the standard approach for implementing systems on ASICs and FPGAs in high performance embedded systems. The principle benefit of these approaches it the ability to re-use existing code. Four example applications are described, and areas where existing library core code is available and helpful, and where there is scope for improvement in availability and standardisation are discussed.