By Topic

An Engineering Approach to Solving HPC Problems using FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
McCormick, A. ; Alpha Data Ltd., Edinburgh

This paper describes the implementation of a number of HPC accelerators on FPGAs. The methodology and tools used for their implementation is the same as the standard approach for implementing systems on ASICs and FPGAs in high performance embedded systems. The principle benefit of these approaches it the ability to re-use existing code. Four example applications are described, and areas where existing library core code is available and helpful, and where there is scope for improvement in availability and standardisation are discussed.

Published in:

Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on

Date of Conference:

5-8 Aug. 2007