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During the development of the Multi-Strip Multi-Gap Resistive Plate Chambers (MMRPCs) for the time-of-flight (ToF) upgrade of the FOPI detector system, we have designed different versions of the front-end electronics (FEE). The signals from a MMRPC are read out on each side of the anode strips by an amplifier followed by a leading-edge discriminator. They are digitized in a time-to-amplitude converter (TAC) followed by a charge-to-digital converter (QDC). These counters are designed to provide a ToF resolution below sigmat les 60 ps requiring an amplifier-diecriminator stage with an intrinsic electronic resolution below sigmat(FEE) les 20 ps. We describe the design steps of the FEE-card from a 4-channel version (FEE1) for the R&D phase to the final 16-channel card (FEE5) for the readout of 4800 channels of the total detector array. Through these design steps we have kept the following key characteristics: low noise sigman les 25 muV RMS (to the amplifier input), high gain (200) and a high bandwidth (1 GHz).