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VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

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4 Author(s)
K. K. Gunnam ; Texas A&M Univ., College Station ; G. S. Choi ; M. B. Yeary ; M. Atiquzzaman

We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2times when compared to the recent state-of-the-art decoder architectures.

Published in:

2007 IEEE International Conference on Communications

Date of Conference:

24-28 June 2007