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High-performance digital ICs manufactured in deep-submicron technologies tend to draw considerable amounts of power during operation. Power droop describes the impact of power consumption transients on the logic values of a circuit's signal lines and, ultimately, on the correctness of the circuit's operation. Although power droop could cause an IC to fail, such failures cannot be screened during testing, because conventional fault models do not cover them. In this article, we present a technique for screening such failures. We propose a heuristic method to generate test sequences that create worst-case power drop by accumulating high- and low-frequency effects. We employ a dynamically constrained version of the classical D-algorithm, which generates new constraints on the fly, for test generation. The obtained patterns can be used for manufacturing test and early silicon validation. We have implemented a prototype ATPG to demonstrate the feasibility of this approach.