By Topic

Design of a High-speed FPGA-based 32-bit Floating-point FFT Processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shengmei Mou ; Nat. Univ. of Defense Technol., Changsha ; Xiaodong Yang

In this paper, we design and implement a 32-bit IEEE 754 single precision floating-point FFT processor. Usually, limited by long pipeline latency of floating-point operations and multi-port RAM access the throughput of FFT processors can only reach approximately one result per cycle. Through making some improvements on the design of butterfly unit and reorganization of the RAM access, almost a throughput of 2 complex results per cycle can be gotten and twice performance as traditional FFT processors can be achieved. As to a 1024-point FFT transform, it can be finished in (512 + 10)*10=5220 cycles.

Published in:

Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing, 2007. SNPD 2007. Eighth ACIS International Conference on  (Volume:1 )

Date of Conference:

July 30 2007-Aug. 1 2007