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This paper presents a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-mum CMOS process. By employing a capacitive-splitting architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX. Provided a 223 - 1 pseudorandom bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage.