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A 20-Gb/s 1 : 2 Demultiplexer With Capacitive-Splitting Current-Mode-Logic Latches

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2 Author(s)
Jun-Chau Chien ; Nat. Taiwan Univ., Taipei ; Liang-Hung Lu

This paper presents a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-mum CMOS process. By employing a capacitive-splitting architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX. Provided a 223 - 1 pseudorandom bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage.

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Microwave Theory and Techniques, IEEE Transactions on  (Volume:55 ,  Issue: 8 )