Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Performance Aware On-Chip Communication Synthesis and Optimization for Shared Multi-Bus Based Architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Pandey, Sujan ; Institute of Microelectronics Systems, Darmstadt University of Technology, Karlstr. 15, D-64283 Darmstadt, Germany. pandey@mes.tu-darmstadt.de ; Glesner, M. ; Muhlhauser, Max

This paper presents a method of on-chip communication topology synthesis and optimization for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate components of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We model the communication behavior of each module as a set of communication lifetime intervals (CLTIs), which are optimized in terms of number of overlaps among them, size of bus width and the minimum number of buses, using ILP (integer linear programming) formulation. We synthesize the communication topology and further optimize the architecture based on the intermodule communication statistics, which are obtained from the system level profiling of an application. The result of applying this approach to the Talking Assistant used in ubiquitous computing application demonstrates the utility of our techniques to synthesize the communication architecture for a complex system.

Published in:

Integrated Circuits and Systems Design, 18th Symposium on

Date of Conference:

4-7 Sept. 2005