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Performance Aware On-Chip Communication Synthesis and Optimization for Shared Multi-Bus Based Architecture

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3 Author(s)
Sujan Pandey ; Institute of Microelectronics Systems, Darmstadt University of Technology, Karlstr. 15, D-64283 Darmstadt, Germany. ; Manfred Glesner ; Max Muhlhauser

This paper presents a method of on-chip communication topology synthesis and optimization for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate components of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We model the communication behavior of each module as a set of communication lifetime intervals (CLTIs), which are optimized in terms of number of overlaps among them, size of bus width and the minimum number of buses, using ILP (integer linear programming) formulation. We synthesize the communication topology and further optimize the architecture based on the intermodule communication statistics, which are obtained from the system level profiling of an application. The result of applying this approach to the Talking Assistant used in ubiquitous computing application demonstrates the utility of our techniques to synthesize the communication architecture for a complex system.

Published in:

2005 18th Symposium on Integrated Circuits and Systems Design

Date of Conference:

4-7 Sept. 2005