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Random Access Memory Faults Descriptions and Simulation using VHDL

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1 Author(s)
Ivaniuk, A.A. ; Belarusian State Univ. of Inf. & Radioelectron., Minsk

This paper describes a new method of random access memory faults description using VHDL language. The fault injection technique, which uses behavioral synthesis VHDL descriptions, is proposed. The injection can be easily automated for memory test algorithms verification using only VHDL language and standard simulation software. No other applications and simulation tools are needed.

Published in:

Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on

Date of Conference:

21-23 June 2007