By Topic

FPGA Based Accelerator for Simulated Annealing with Greedy Perturbations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
M. Lukowiak ; Computer Engineering Department, Rochester Insistute of Technology, 83 Lomb Memorial Drive, Rochester, NY 14623, USA. E-mail: ; B. Cody

This paper discusses design of an field programmable gate array (FPGA) based hardware accelerator for a standard cell placement tool. A software program was used to determine the bottlenecks in the simulated annealing (SA) algorithm with greedy perturbations and dynamic cooling schedule. A solution implementing computing platform with specialized hardware configurations inside an FPGA was investigated as having the possibility to improve the efficiency of the SA-based algorithms.

Published in:

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

Date of Conference:

21-23 June 2007