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FPGA Based Accelerator for Simulated Annealing with Greedy Perturbations

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2 Author(s)
M. Lukowiak ; Computer Engineering Department, Rochester Insistute of Technology, 83 Lomb Memorial Drive, Rochester, NY 14623, USA. E-mail: mxleec@rit.edu ; B. Cody

This paper discusses design of an field programmable gate array (FPGA) based hardware accelerator for a standard cell placement tool. A software program was used to determine the bottlenecks in the simulated annealing (SA) algorithm with greedy perturbations and dynamic cooling schedule. A solution implementing computing platform with specialized hardware configurations inside an FPGA was investigated as having the possibility to improve the efficiency of the SA-based algorithms.

Published in:

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

Date of Conference:

21-23 June 2007