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A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process

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2 Author(s)

This paper presents a kick-back reduced comparator based on a sense-amplifier type comparator. The kickback charge and resulting voltage peak is reduced by 6times, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90 nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.

Published in:

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

Date of Conference:

21-23 June 2007