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Interconnect RC delay, predominantly affected by the effective dielectric constant (k-value) and by the copper resistivity (rhoCu), is an important performance metric for back-end-of-line (BEOL) process assessment. As process technology scales, interpretation of fundamental process-induced RC delay variations becomes a challenge as the relative importance of statistical process-induced fluctuations (variation of critical dimensions during plasma etching of low-k materials, line profiles, thickness nonuniformity, etc.) grows rapidly and begins to show. A more accurate interpretation of experimental data and prediction of future performance trends requires a more realistic assessment that accounts for such statistical fluctuations. In this paper, an inventory of the most common possible sources of statistical process-induced RC delay variations is made, parameterized, and subsequently used to generate a realistic 2-D interconnect model from which, R and C, and thereby RC delay, are computed. For both wire resistivity and RC, response surface models (RSM) are subsequently generated based on the results of a full factorial design-of-experiment analysis with these input parameters. Finally, based on the RSMs, an improved methodology of interconnect performance evaluation is proposed.