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Low Power Design of High Performance Memory Access Architecture for HDTV Decoder

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2 Author(s)
Tsun-Hsien Wang ; Information & Communications Research Laboratories, Industrial Technology Research Institute, Hsin-Chu, Taiwan, R.O.C. Email: thwang@itri.org. tw ; Ching-Te Chiu

To improve memory access efficiency and to reduce power consumption in HDTV video decoders, we propose a novel memory address mapping method and an efficient memory accessing architecture. The memory address mapping enables a computation-free memory address generation from the logical address of the data word in a video frame. The simple address generation is achieved by combining neighboring macroblocks into groups and stores the group of macroblocks in the same row of the external memory. By grouping suitable macroblocks, depending on interlaced or progressive scanning, we significantly reduce the cross-row memory accessing in the external memory, which is both time consuming and power consuming. In the memory accessing architecture, we rearrange the access order of luminance and chrominance data in motion compensations to further reduce the number of row changes of the external memory. Our analysis shows that the number of row changes is reduced by 87.67% and throughput of our memory-accessing scheme is improved by 30.91% compared to conventional approaches.

Published in:

2007 IEEE International Conference on Multimedia and Expo

Date of Conference:

2-5 July 2007