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Design of algorithm-based fault-tolerant VLSI array processor

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2 Author(s)
C. -M. Liu ; Inst. of Electron., Chiao Tung Univ., Hsinchu, Taiwan ; C. -W. Jen

A systematic design methodology which maps a matrix arithmetic algorithm to a fault-tolerant array processor with different topologies and dimensions is presented. The design issues to be addressed in the method are: (a) how to derive a VLSI array with different topologies and dimensions from the algorithm; (b) how to distribute the data processing to the PEs so that a faulty PE will result in limited erroneous data on which the checking scheme is valid. Two examples, matrix multiplication and Givens reduction, are used to illustrate this design method.

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IEE Proceedings E - Computers and Digital Techniques  (Volume:136 ,  Issue: 6 )