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In this paper, modeling and predictive simulations of advanced junction formation for CMOS devices based on atomistic kinetic Monte Carlo (kMC) process simulator are presented. First, we will briefly discuss the different challenges and alternatives for the formation of advanced ultra-shallow junctions for the forthcoming generation of CMOS devices. We will present the physical atomistic modeling used in term of damage evolution, dopant diffusion and clustering, interaction with interfaces and the impact of impurities, which are crucial for accurate simulations. Subsequently, comparisons with a wide range of SIMS, sheet resistance measurement as well as electrical device characteristics showed that experimental results were remarkably well reproduced by the simulations. Finally, we shall demonstrate that device optimization can be achieved based on kMC process simulations, even for novel co- implant processes. This paves the way for the use of kMC in the design of devices and the optimization of junction formation to improve device performance.