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Novel Approach to Reduce Source/Drain Series and Contact Resistance in High-Performance UTSOI CMOS Devices Using Selective Electrodeless CoWP or CoB Process

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6 Author(s)
Pan, J. ; Advanced Micro Devices, Inc./IBM Alliance, Yorktown Heights ; Topol, A. ; Shao, I. ; Chun-Yung Sung
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This letter reports a selective metal deposition process using an electrodeless technique for MOSFETs fabricated in an ultrathin silicon-on-insulator (UTSOI) substrate. A layer of metal (CoWP or CoB) is formed on the source and drain nickel and cobalt silicides without depositing on the dielectric spacers. Leakage current information, which is an indication of selectivity of the process, is presented in this letter. The shortest channel length of the UTSOI NMOSFETs is 20 nm, and the SOI thickness is 10 nm. The data show that excellent selectivity is achieved without increasing the leakage current of the transistors.

Published in:

Electron Device Letters, IEEE  (Volume:28 ,  Issue: 8 )

Date of Publication:

Aug. 2007

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