Skip to Main Content
In this letter, a post-CMOS selectively grown porous silicon (SGPS) technique is proposed to improve the Q-factor of the integrated inductor. The inductors are fabricated in a standard RF CMOS process, and porous silicon layers are selectively grown after processing from the backside of the silicon wafer. For a 2.1-nH inductor fabricated in a 1 poly 3 metal 0.35- RF CMOS process, a 105% increase (from 9.5 to 19.4) in peak -factor is achieved. Furthermore, a 2.45-GHz CMOS voltage-controlled oscillator using the proposed SGPS inductor achieves 7.2-dBc phase noise improvement at 100-kHz frequency offset. The characteristics of the SGPS substrate have been extracted using the conventional lump element model, which shows that our SGPS technique increases the substrate impedance by one order magnitude without disturbing the inductor value. These results demonstrate that our post-CMOS SGPS technique is very promising for RF integrated circuit applications.