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Design for Testability of CMOS Analog Sum-Product Error-Control Decoders

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4 Author(s)

A built-in self-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:54 ,  Issue: 8 )