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Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units

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4 Author(s)

Leading zero anticipation with error correction is a widely adopted technique in the implementation of high-speed IEEE-754-compliant floating-point units (FPUs), which are critical for area and power in multimedia-oriented systems-on-chips. We investigated a novel LZA algorithm allowing us to remove error correction circuitry by reducing the error rate below a commonly accepted limit for image processing applications, which is not achieved by previous techniques. We embedded our technique into a complete FPU definitely obtaining both area saving and overall FPU latency reduction with respect to traditional designs.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 8 )

Date of Publication:

Aug. 2007

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