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We diagnosed circuits to identify of margin reduction mechanisms in large-scale SFQ circuits. Two types of shift registers with partial or full bias line shields were designed and tested. We investigated the locations and origins of circuit errors by measuring bias margins and output waveforms. The results indicated that bias line currents can degrade the bias margin around the periphery in large-scale circuits with partial bias line shields. On the other hand, no apparent reduction of bias margins was observed in any part of the circuit area in the circuits with full bias line shields. However, we observed a reduction of the bias margin due to flux trapping even when we used a completely non-magnetic He dewar surrounded by a dual-layer permalloy metal shield. We found that the probability of finding a defect in a circuit with 10,000 Josephson junctions is less than 60%.