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This paper proposes a method to perform failure mode and effects analysis (FMEA) on system-on- chips (SoC). An automatic tool extracts information from the SoC description and uses them to estimate the intrinsic criticality of invariant and elementary "sensitive zones " and to compute metrics such failure rates, safe failures fraction and diagnostic coverage. A validation flow based on fault injection and fault simulation is included to cross check the FMEA.
Date of Conference: 8-11 July 2007