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Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics

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4 Author(s)
Partha Pratim Pande ; Washington State University, USA ; Amlan Gangul ; Brett Feero ; Cristian Grecu

Three dimensional (3D) network on chip (NoC) has attracted researchers' attention recently. 3D NoCs are capable of achieving better system throughput and lower latency compared to the corresponding 2D implementations. To fully exploit the performance benefits of 3D architectures, it is imperative to address signal integrity issues in the design phase and its implications on energy dissipation. In this work we show that by incorporating joint crosstalk avoidance and multiple error correction schemes it is possible to enhance the robustness and reduce the energy dissipation simultaneously for both the 3D and more conventional planar NoC architectures. The achievable energy savings in 3D NoCs is significantly more than that in 2D structures.

Published in:

13th IEEE International On-Line Testing Symposium (IOLTS 2007)

Date of Conference:

8-11 July 2007