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This paper addresses the lot scheduling problem in the semiconductor wafer fabrication facilities. We provide a simulation study to examine the performance of sixteen existing dispatching rules on the tardy rate, mean tardiness, and the maximum tardiness. A public and representative test bed, the MIMAC (measurement and improvement of manufacturing capacities) test bed is used. The best rules with respect to each objective are identified through the experiments, and some findings are provided to be guidelines for designing new dispatching rules.