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A mux-based High-Performance Single-Cycle CMOS Comparator

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2 Author(s)
Hing-Mo Lam ; Hong Kong Univ. of Sci. & Technol., Hong Kong ; Chi-ying Tsui

In this brief, a new architecture for high-fan-in CMOS comparator is proposed. The architecture is based on a hierarchical two-stage comparator structure and a dynamic MUX is used instead of a comparator in the second stage of the structure. By doing so, the fast dynamic MUX significantly improves the overall delay of the high-fan-in comparators. At the same time, a novel high-performance static priority encoder is proposed to generate the control signal for the MUX. A 64-bit MUX-based comparator has been built and compared with the existing fastest single-cycle design in the study by Lam and Tsui (2006). From both the post-layout simulation and test-chip measurement results, it is shown that the performance is improved by around 28%.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 7 )

Date of Publication:

July 2007

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