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Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated in 0.13-mum CMOS bulk technology show that our power gating structure yields an expanded design space with more power-performance tradeoff alternatives.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:54 , Issue: 7 )
Date of Publication: July 2007