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A 62.5–625-MHz Anti-Reset All-Digital Delay-Locked Loop

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3 Author(s)
Shao-Ku Kao ; Nat. Taiwan Univ., Taipei ; Bo-Jiun Chen ; Shen-Iuan Liu

An anti-reset all-digital delay-locked loop (DLL) is presented. When the input clock frequency changes significantly, the dynamic frequency detector re-locks the DLL without any external reset signal. The proposed binary time-to-digital converter (BTDC) reduces effectively the hardware, compared with a conventional TDC. Unlike many previous all-digital DLLs, this one is a closed feedback loop that can track environmental variations. The input frequency range can be operated from 62.5-625 MHz. It spends at most six cycles to synchronize the input and output clocks.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:54 ,  Issue: 7 )