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A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator

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2 Author(s)
Kuo-Hsing Cheng ; Nat. Central Univ., Nanjing ; Yu-Lung Lo

This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm2) and dissipates less power (15 mW) than other wide-range DLLs.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 7 )