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Hierarchical Value Cache Encoding for Off-Chip Data Bus

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3 Author(s)
Chung-Hsiang Lin ; Dept. of Comput. Sci. & Inf. Eng., National Taiwan Univ., Taipei ; Chia-Lin Yang ; Ku-Jei King

Off-chip data bus consumes a significant part of system power. Recent works use small caches (value cache) at each side of the off-chip data bus, and transmit cache indexes instead of data values to reduce bus switching activity. A larger VC has a higher VC hit rate, but it also incurs more switching activity on a VC hit. In this paper, we propose the hierarchical VC design concept that provides a good tradeoff between VC capacity and bus switching activity. Our experimental results show that the proposed hierarchical VC design reduces the off-chip data bus energy by 60.2%

Published in:

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Date of Conference:

4-6 Oct. 2006

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