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A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

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3 Author(s)
Kil, J. ; Intel Corp., Folsom, CA ; Jie Gu ; Kim, C.H.

This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network using the proposed drivers shows an 89% reduction in 3sigma clock skew value. A 0.4V test chip has been fabricated in a 0.18mum 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6times faster switching speed and 2.4times less delay sensitivity under temperature variations

Published in:

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Date of Conference:

4-6 Oct. 2006