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Energy-Efficient Dynamic Instruction Scheduling Logic through Instruction Grouping

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3 Author(s)
Sasaki, H. ; Res. Center for Adv. Sci. & Technol., Tokyo Univ. ; Kondo, M. ; Nakamura, H.

Dynamic instruction scheduling logic is quite complex and dissipates significant energy in microprocessors that support superscalar and out-of-order execution. We propose a novel microarchitectural technique to reduce the complexity and energy consumption of the dynamic instruction scheduling logic. The proposed method groups several instructions as a single issue unit and reduces the required number of ports and the size of the structure for dispatch, wakeup, select, and issue. The present paper describes the microarchitecture mechanisms and shows evaluation results for energy savings and performance. These results reveal that the proposed technique can greatly reduce energy with almost no performance degradation, compared to the conventional dynamic instruction scheduling logic

Published in:

Low Power Electronics and Design, 2006. ISLPED'06. Proceedings of the 2006 International Symposium on

Date of Conference:

4-6 Oct. 2006