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Optimization and Elimination of Parasitic Latchup in Advanced Smart-Power Technologies

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4 Author(s)
Khemka, V. ; Freescale Semicond. Inc., Tempe ; Ronghua Zhu ; Bose, A. ; Roggenbauer, T.

This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart-power technology. The impact of logic ground isolation from the substrate and the presence p+ and n+ buried layers below the logic wells is quantified. Four different types of structures have been studied and it is demonstrated that certain ion-implantation layers that are inherently available in a standard deep submicron smart-power process due to medium and high-voltage requirements can be effectively utilized to optimize and improve the latchup performance of standard CMOS.

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Device and Materials Reliability, IEEE Transactions on  (Volume:7 ,  Issue: 1 )