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This paper presents a study using alpha- and neutron-accelerated tests to characterize the soft error rate (SER) of flip-flops (FFs) that are used in 90-nm CMOS production designs. The investigated FFs differ in circuit schematic, threshold voltage (VT), drive strength, and cell height. Both the alpha- and the neutron-induced SER of FFs on a dedicated 90-nm test chip showed a strong dependence on clock and data state. Theoretical results demonstrate that the FF SER is modeled best if particle hits at both the NMOS and the PMOS drains are included and if the resulting current pulse is assumed to have a width of approximately 5 ps. Furthermore, the impact of process variations on the FF SER is shown to depend strongly on the data state and on the applied pulsewidth. On average, the SER per bit of the investigated FFs is higher than the typical SER per bit of unprotected static random access memories in 90 nm and has increased with a factor of 3 per technology generation. The reported results illustrate the importance of the characterization of FF SER in order to design reliable integrated circuits.