Nanoscale and device level reliability of high-k dielectrics based CMOS nanodevices

In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO
₂
layers on the degradation of HfO
₂
/SiO
₂
gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of the electrical stress on the SiO
₂
and HfO
₂
layers. Both kinds of tests show that the SiO
₂
interfacial layer plays an important role in the degradation and breakdown of high-k gate stacks in CMOS advanced nanodevices.