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Good understanding of power loss in a high frequency synchronous buck converter is important for design optimization of both discrete and system level. Most of the power losses are relatively easy to quantify. The exception is the power loss associated with Cdv/dt induced turn on of the low-side metal oxide semiconductor field effect transistor (synchronous rectifier). This paper characterizes the Cdv/dt induced power loss in two ways. First, detailed device characterization, in-circuit testing, and modeling are used for a comparative loss calculation. This method offers detailed loss breakdown but requires specialized test equipment and is rather complicated and time consuming. A simple method is then introduced to accurately quantify the Cdv/dt loss. With this method, the Cdv/dt induced power loss on synchronous buck converters at different operation conditions can be readily assessed. The impacts of Cdv/dt induced loss on different applications are addressed. Finally, the design tradeoffs at both discrete and system levels are discussed.