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A compact novel input offset compensation scheme with reduced sensitivity to charge injection and leakage is introduced. It stores an amplified version of the offset that is applied during normal operation on the input side through a capacitive divider. Offset compensation takes place in a voltage additive manner in a separate path from the input signal. Experimental results of a MOSIS test chip fabricated in 0.5 mum AMI CMOS technology are shown that validate the proposed scheme.