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Compact Novel Floating Gate Offset Compensation Scheme with Low Sensitivity to Charge Injection, Clock Feedthrough and Leakage

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5 Author(s)
Annajirao Garimella ; Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003, USA. annaji@nmsu.edu ; Lalitha Mohana Kalyani-Garimella ; Jaime Ramirez-Angulo ; Ramon G. Carvajal
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A compact novel input offset compensation scheme with reduced sensitivity to charge injection and leakage is introduced. It stores an amplified version of the offset that is applied during normal operation on the input side through a capacitive divider. Offset compensation takes place in a voltage additive manner in a separate path from the input signal. Experimental results of a MOSIS test chip fabricated in 0.5 mum AMI CMOS technology are shown that validate the proposed scheme.

Published in:

2006 49th IEEE International Midwest Symposium on Circuits and Systems  (Volume:1 )

Date of Conference:

6-9 Aug. 2006