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The capability of 90 nm CMOS technology for low-power RF front-ends is demonstrated using fully integrated low power low noise amplifiers. This paper presents a 5.25 GHz high linearity, high gain LNA design for a receiver architecture based on IEEE802.16a WMAN standard. First, we go through the standard in order to obtain the receiver specifications. Next we choose a suitale arcitecture for our receiver and simulate it using ADS cad tool to extract the specifications which are needed for the low noise amplifier. Finally we design our LNA based on the design method of Mr. D. K. Shaefer, also we improve the Greenhouse spiral inductor model and optimize it employing a random search algorithm named Simulated Annealing. The targeted frequency band is the unlicensed band UNII 5 GHz. The LNA achieves voltage gain of 24 dB, noise figure of 1.8 dB, the IIP3 of 7.5 dBm, and the reverse isolated is about -11.6. Employing the 90 nm CMOS process, the LNA dissipates 1.75 mW using a 1.2 V supply voltage.
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on (Volume:1 )
Date of Conference: 6-9 Aug. 2006