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This paper presents a new algorithm for progressive image coding, called tag setting in hierarchical tree (TSIHT). The TSIHT coding can save the memory requirement while keeping the low-bit-rate quality high. The TSIHT algorithm has been implemented onto a chip with 0.35 mu 1P4M CMOS technology. The chip can handle 256times256 gray-scale images and the gate count is about 2560 gates within 247500 mum2 area. The latency of the critical path is 6.32 ns, and the maximum working frequency can be as high as 158 MHz.