By Topic

Characterization of Strained Silicon MOSFET Using Semiconductor TCAD Tools

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wong Yah Jin ; Univ. of Teknologi Malaysia, Skudai ; Saad, I. ; Ismail, R.

The paper is looking into the enhancement of conventional PMOS by incorporating a strained silicon within the channel and bulk of semiconductor. A detailed 2D process simulation of strained silicon PMOS (SSPMos) and its electrical characterization was done using TCAD tool. With the oxide thickness, Tox of 16 nm and germanium concentration of 35%, the threshold voltage Vt for the strained Si and conventional PMOS is -0.5067V and -0.9290V respectively. This indicates that the strained silicon had lower power consumption. Beside that, the drain induced barrier lowering (DIBL) value for the strained PMOS is 0.3034V and the conventional PMOS is 0.4747V, which shows a better performance for strained silicon as compared to conventional PMOS. In addition, the output characteristics were also obtained for SSPMos which showed an improvement of drain current compared with conventional PMOS.

Published in:

Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on

Date of Conference:

Oct. 29 2006-Dec. 1 2006