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This paper presents the design and simulation of high speed, high gain and low power fully differential operational amplifier (op-amp) implemented in 0.35 um CMOS technology. The op-amp was designed for sample-and-hold stage of 100 mW 10-bit 50 MS/s pipelined analog-to-digital converter. A topology of single-stage folded-cascode with gain boosting technique is employed in this op-amp. The simulated op-amp achieves a DC gain of 95dB, unity gain bandwidth of 412 MHz and phase margin of 75 degrees. The settling time is 7.5 ns and the op-amp consumes power 12.8 mW with supply voltage of 3V.