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Design of Single-Stage Folded-Cascode Gain Boost Amplifier for 100mW 10-bit 50MS/s Pipelined Analog-to-Digital Converter

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4 Author(s)
Musa, R. ; AMS IC Design Group, Berhad ; Yusoff, Y. ; Tan Kong Yew ; Ahmad, M.R.

This paper presents the design and simulation of high speed, high gain and low power fully differential operational amplifier (op-amp) implemented in 0.35 um CMOS technology. The op-amp was designed for sample-and-hold stage of 100 mW 10-bit 50 MS/s pipelined analog-to-digital converter. A topology of single-stage folded-cascode with gain boosting technique is employed in this op-amp. The simulated op-amp achieves a DC gain of 95dB, unity gain bandwidth of 412 MHz and phase margin of 75 degrees. The settling time is 7.5 ns and the op-amp consumes power 12.8 mW with supply voltage of 3V.

Published in:

Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on

Date of Conference:

Oct. 29 2006-Dec. 1 2006