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This paper proposes a novel fully parallel FFT architecture based on canonical signed digit (CSD) multiplier-less targeting wireless communication applications, such as IEEE802.15.3a wireless personal area network (WPAN) baseband. The proposed architecture has the advantages of high throughput, less latency, and smaller area. The multiplier-less architecture uses shift- and-add operations to realize the complex multiplier and uses the CSD to optimize these operations. The design has been coded in Verilog HDL targeting Xilinx Virtex-II FPGA series. It is fully implemented and tested on real hardware using Virtex-II FG456 prototype board. Based on this architecture, the implementation of 8-points FFT on Virtex-II can run at a maximum clock frequency of about 400 MHz which lead to about 3.2 GS/s throughput with a latency of 6 clock cycles using 16,580 equivalent gates. Comparison with a conventional parallel architecture design of the same size can run only at a maximum clock frequency of 220 MHz or 1.76 GS/s throughput with a latency of 12 clock cycles using 77,418 equivalent gates for the design. The resulting throughput increases by about 82% while the equivalent gates and latency decrease by about 79% and 50% respectively.
Date of Conference: Oct. 29 2006-Dec. 1 2006