Skip to Main Content
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address a structured ASIC architecture fabric directly tie to FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. Our goal is to leverage the power/delay/area benefits of structured ASIC technology vs. FPGA with a simple flow which maintains the benefits of FPGAs for ease of test, prototyping, characterization and pre-verification. We will go over the introduction of FPGA to structured-ASIC migration, the architecture of the logic fabric follow by the Lcell to Hcell mapping methodology which can eliminate the need of complicated verification effort and overview of the CAD flow.