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A 10.8-GHz CMOS Low-Noise Amplifier Using Parallel-Resonant Inductor

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4 Author(s)
Kuo-Jung Sun ; Nat. Taiwan Univ., Taipei ; Zuo-Min Tsai ; Kun-You Lin ; Huei Wang

A noise-reduction design method using parallel-resonant technique is demonstrated to improve the noise performance of a 10-GHz CMOS cascode low-noise amplifier, which is designed and implemented in a standard mixed-signal/RF bulk 0.18-mum CMOS technology. Measurements show a power gain of 10 dB with noise figure of 2.5 dB at 10.8 GHz, which is believed to be the lowest NF among the LNAs using bulk 0.18 mum CMOS at this frequency.

Published in:

Microwave Symposium, 2007. IEEE/MTT-S International

Date of Conference:

3-8 June 2007