A 10.8-GHz CMOS Low-Noise Amplifier Using Parallel-Resonant Inductor

A noise-reduction design method using parallel-resonant technique is demonstrated to improve the noise performance of a 10-GHz CMOS cascode low-noise amplifier, which is designed and implemented in a standard mixed-signal/RF bulk 0.18-μm CMOS technology. Measurements show a power gain of 10 dB with noise figure of 2.5 dB at 10.8 GHz, which is believed to be the lowest NF among the LNAs using bulk 0.18 μm CMOS at this frequency.