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A Smart Load-Pull Method to Safely Reach Optimal Matching Impedances of Power Transistors

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5 Author(s)
T. Reveyrand ; XLIM, C2S2 Department, UMR CNRS 6172, 123 Av. A. Thomas, 87060 Limoges Cedex, France ; T. Gasseling ; D. Barataud ; S. Mons
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This paper presents a new method to find optimal load impedances of power transistors with a VNA based Load-Pull measurement setup. Most of load pull setups find the optimal load impedance of a device under test (DUT) for a given available input power. If the optimal impedance must satisfy a trade off between several parameters, such as gain compression or power added efficiency, the measurement procedure may become very time consuming. Our method automatically generates a behavioral model of the DUT. Crossing-informations from this model and measurements lead us to the good impedance optimum with a limited number of iterations.

Published in:

2007 IEEE/MTT-S International Microwave Symposium

Date of Conference:

3-8 June 2007