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A strategy to design high-speed low-power MOS current-mode logic (MCML) static frequency dividers is here proposed. Analytical criteria to exploit the speed potential of MCML gates are first introduced. Then, analytical criteria are formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, reducing the overall power consumption. The analytical approach allows for a deeper understanding of the power-delay trade-off involved in the design. In order to validate the theoretical derivations, SPICE simulation results on a 1:8 frequency divider by using a 0.18-mum CMOS process are given.