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An Efficient Hardware Implementation of a Robust and Low-Complexity ADSRC Timing Synchronization Design

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4 Author(s)

In this paper, a robust, low-complexity timing synchronization algorithm suitable for 5.9 GHz advanced dedicated short range communications (ADSRC) system and its efficient hardware implementation is proposed. Cross-correlation technique is used to detect the starting point of short training symbol and the guard interval of the long training symbol. The design is implemented in a Xilinx Vertex-II XC2V2000 field programmable gate array (FPGA). Synchronization Error Rate results of Matlab and post-layout simulation show that the proposed algorithm is robust and efficient in high-mobility environments.

Published in:

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Date of Conference:

10-13 Dec. 2006