By Topic

Design and Implementation in FPGA of a MIMO Decoder for a 4G Wireless Receiver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jimenez-Pacheco, A. ; Univ. Politecnica de Madrid, Madrid ; Fernandez-Herrero, A. ; Casajus-Quiros, J.

In this paper we address the implementation in FPGAs of a multiple-input multiple-output (MIMO) decoder embedded in a prototype of a 4G mobile receiver. This MIMO decoder is part of a multi-carrier code-division multiple-access (MC-CDMA) radio system, equipped with multiple antennas at both ends of the link, that is able to handle up to 32 users and provides raw transmission bit-rates up to 125 Mbps. The task of the MIMO decoder is to appropriately combine the signals simultaneously received on all antennas to construct an improved signal, free from interference, from which to estimate the transmitted symbols. A comprehensive explanation of the complete design process is provided, including architectural decisions, floating-point to fixed-point translation and description of the validation procedure. Implementation results using FPGA devices of the Xilinx Virtex-4 family are also reported.

Published in:

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Date of Conference:

10-13 Dec. 2006