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This paper presents a theoretical analysis of the maximum frequency of operation of CMOS static frequency dividers. The approach is based on the transient analysis of output voltages derived from differential equations of the large-signal model of the circuit. Tradeoffs and design techniques for very high frequency dividers have been discussed on the basis of the derived expression. An inductor-less 45 GHz divider and a shunt-peaked 60 GHz divider have been designed in 0.13 mum process following the suggested design techniques. Detailed simulation results have been presented.