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This paper presents an optimized design of a high-speed digital IQ demodulator intended for the implementation of the feedback path of an adaptive base band pre-distorter (DPD). Indeed, the optimization of the DPD linearization capability in terms of correction bandwidth and nonlinearity effects minimization is directly related to the accuracy and speed of the IQ demodulator. In this work, a digital IQ demodulator is designed, optimized and implemented in a Xilinx FPGA device. This allowed a high speed processing of about 200MHZ with a substantial reduction of the FPGA used gates.